In the manufacture of integrated circuits, interconnects are generally formed on a semiconductor substrate using a copper dual damascene process. Such a process typically begins with a trench being etched into a dielectric layer and then filled with a barrier/adhesion layer and a seed layer using a physical vapor deposition (PVD) sputtering process. An electroplating process is then used to fill the via and trench with copper metal to form the interconnect. However, as device dimensions scale down and the features become narrower, the aspect ratio of the features becomes more aggressive. Typically, there is a plurality of vias within a given layer of an integrated circuit structure. Vias in one area of the structure can be connected to vias or interconnects in other areas of the structure by routing through one or more subsequent dielectric layers.